An Automated Recipe-Based Defect Analysis System for ASICs

40 Manufacturers of application-specific integrated circuits (ASICs) face some unique yield-management challenges. At any given time, scores of different products and numerous different technologies may be moving through the manufacturing line – some ramping up, some already ramped, and some in a start-up phase. While any competitive semiconductor company must constantly refine and improve its defect detection and correction methodologies, an ASIC house is unmatched in its need for yield management methodologies that are simultaneously broad-based and robust. In this paper, LSI Logic describes how implementing a recipe-based defect analysis system has simplified management of their inline monitoring program, and accelerated yield learning by providing faster detection of defect excursions and faster, more reliable lot dispositions. Defect Reduction F E A T U R E S